00001 #ifndef _ALT_BPP_IMPL_H
00002 #define _ALT_BPP_IMPL_H
00003
00004 #ifdef __cplusplus
00005 extern "C" {
00006 #endif
00007
00008
00009
00010
00011 struct bpp_reg {
00012 uint32_t dma_csr;
00013 uint32_t dma_addr;
00014 uint32_t dma_bcnt;
00015 uint32_t dma_tst_csr;
00016
00017 uint16_t hw_config;
00018 uint16_t op_config;
00019
00020 uint8_t data;
00021 uint8_t trans_cntl;
00022 uint8_t out_pins;
00023 uint8_t in_pins;
00024
00025 uint16_t int_cntl;
00026 };
00027
00028
00029
00030
00031
00032
00033
00034
00035 const uint32_t BPP_INT_PEND = 1;
00036 const uint32_t BPP_ERR_PEND = 1<< 1;
00037 const uint32_t BPP_DRAINING = (1<< 3)|(1<< 2);
00038 const uint32_t BPP_INT_EN = 1<< 4;
00039 const uint32_t BPP_FLUSH = 1<< 5;
00040 const uint32_t BPP_SLAVE_ERR = 1<< 6;
00041 const uint32_t BPP_RESET_BPP = 1<< 7;
00042 const uint32_t BPP_READ = 1<< 8;
00043 const uint32_t BPP_ENABLE_DMA = 1<< 9;
00044 const uint32_t BPP_ENABLE_BCNT = 1<<13;
00045 const uint32_t BPP_TERMINAL_CNT = 1<<14;
00046 const uint32_t BPP_BURST_SIZES_MASK= (1<<18)|(1<<19);
00047 const uint32_t BPP_DRAIN_DISABLE = 1<<20;
00048 const uint32_t BPP_TC_INTR_DISABLE = 1<<23;
00049 const uint32_t BPP_EN_CHAIN_DMA = 1<<24;
00050 const uint32_t BPP_DMA_ON = 1<<25;
00051 const uint32_t BPP_ADDR_VALID = 1<<26;
00052 const uint32_t BPP_NEXT_VALID = 1<<27;
00053 const uint32_t BPP_DEVICE_ID_MASK = 0xf0000000;
00054
00055
00056
00057 const uint16_t BPP_DSS_SIZE = (1<< 6)|(1<< 5)|(1<< 4)|(1<< 3)|(1<< 2)|(1<<1)| 1;
00058 const uint16_t BPP_DSW_SIZE = (1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8);
00059 const uint16_t BPP_CNTR_TEST= (1<<15);
00060
00061
00062
00063 const uint16_t BPP_EN_VERSATEC = 1;
00064 const uint16_t BPP_VERSATEC_INTERLOCK= 1<< 1;
00065 const uint16_t BPP_IDLE = 1<< 3;
00066 const uint16_t BPP_SRST = 1<< 7;
00067 const uint16_t BPP_ACK_OP = 1<< 8;
00068 const uint16_t BPP_BUSY_OP = 1<< 9;
00069 const uint16_t BPP_EN_DIAG = 1<<10;
00070 const uint16_t BPP_ACK_BIDIR = 1<<11;
00071 const uint16_t BPP_BUSY_BIDIR = 1<<12;
00072 const uint16_t BPP_DS_BIDIR = 1<<13;
00073 const uint16_t BPP_DMA_DATA = 1<<14;
00074 const uint16_t BPP_EN_MEM_CLR = 1<<15;
00075
00076
00077
00078 const uint8_t BPP_DS_PIN = 1;
00079 const uint8_t BPP_ACK_PIN = 1<< 1;
00080 const uint8_t BPP_BUSY_PIN = 1<< 2;
00081 const uint8_t BPP_DIRECTION = 1<< 3;
00082
00083
00084
00085 const uint8_t BPP_SLCTIN_PIN = 1;
00086 const uint8_t BPP_AFX_PIN = 1<< 1;
00087 const uint8_t BPP_INIT_PIN = 1<< 2;
00088
00089
00090
00091 const uint8_t BPP_ERR_PIN = 1;
00092 const uint8_t BPP_SLCT_PIN = 1<< 1;
00093 const uint8_t BPP_PE_PIN = 1<< 2;
00094
00095
00096
00097 const uint16_t BPP_ERR_IRQ_EN = 1;
00098 const uint16_t BPP_ERR_IRP = 1<< 1;
00099 const uint16_t BPP_SLCT_IRQ_EN= 1<< 2;
00100 const uint16_t BPP_SLCT_IRP = 1<< 3;
00101 const uint16_t BPP_PE_IRQ_EN = 1<< 4;
00102 const uint16_t BPP_PE_IRP = 1<< 5;
00103 const uint16_t BPP_BUSY_IRQ_EN= 1<< 6;
00104 const uint16_t BPP_BUSY_IRP = 1<< 7;
00105 const uint16_t BPP_ACK_IRQ_EN = 1<< 8;
00106 const uint16_t BPP_DS_IRQ_EN = 1<< 9;
00107 const uint16_t BPP_ERR_IRQ = 1<<10;
00108 const uint16_t BPP_SLCT_IRQ = 1<<11;
00109 const uint16_t BPP_PE_IRQ = 1<<12;
00110 const uint16_t BPP_BUSY_IRQ = 1<<13;
00111 const uint16_t BPP_ACK_IRQ = 1<<14;
00112 const uint16_t BPP_DS_IRQ = 1<<15;
00113 #define BPP_ALL_IRQS (BPP_ERR_IRQ | BPP_SLCT_IRQ | BPP_PE_IRQ | BPP_BUSY_IRQ \
00114 | BPP_ACK_IRQ | BPP_DS_IRQ)
00115
00116 #ifdef __cplusplus
00117 }
00118 #endif
00119
00120 #endif