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bppimpl.h

Go to the documentation of this file.

#ifndef _ALT_BPP_IMPL_H
#define _ALT_BPP_IMPL_H

#ifdef __cplusplus
extern "C" {
#endif

/* Hardware registers for bpp device.
   N.B. nothing declared volatile, so we MUST use the DDI access routines.
   The original version is in /usr/include/sys/bpp_reg.h */
struct bpp_reg {
   uint32_t dma_csr;     /* DMA control and status register */
   uint32_t dma_addr;    /* address register */
   uint32_t dma_bcnt;    /* byte count register */
   uint32_t dma_tst_csr; /* DMA2 test control/status register */

   uint16_t hw_config;   /* hardware configuration register */
   uint16_t op_config;   /* operation configuration register */

   uint8_t  data;        /* parallel port data */
   uint8_t  trans_cntl;  /* transfer control register */
   uint8_t  out_pins;    /* output pins register */
   uint8_t  in_pins;     /* input pins register */

   uint16_t int_cntl;    /* interrupt control register */
};

/* In the bit definitions that follow, some don't apply to the current
   hardware, but may go back to a much earlier bpp driver, written by
   Deborah Gronke Bennett about ten years ago.
*/

/* Cf. /usr/include/sys/bpp_reg.h  for the original version. */
/* Bits in the dma_csr register */
const uint32_t BPP_INT_PEND        = 1;     /*  -> DMA or control intr. pending */
const uint32_t BPP_ERR_PEND        = 1<< 1; /*  -> SBus error pending */
const uint32_t BPP_DRAINING        = (1<< 3)|(1<< 2); /* -> cache is draining */
const uint32_t BPP_INT_EN          = 1<< 4; /* <-> Enable interrupts */
const uint32_t BPP_FLUSH           = 1<< 5; /* <-  Flush the cache */
const uint32_t BPP_SLAVE_ERR       = 1<< 6; /* <=> Slave cycle size error */
const uint32_t BPP_RESET_BPP       = 1<< 7; /* <-> Hardware reset parallel port */
const uint32_t BPP_READ            = 1<< 8; /*  -> 1 == DMA read, 0 == DMA write */
const uint32_t BPP_ENABLE_DMA      = 1<< 9; /* <-> Enable DMA transfers */
const uint32_t BPP_ENABLE_BCNT     = 1<<13; /* <-> Enable byte counter in DMA */
const uint32_t BPP_TERMINAL_CNT    = 1<<14; /* <=> Terminal count flag */
const uint32_t BPP_BURST_SIZES_MASK= (1<<18)|(1<<19); /* <-> SBus burst sizes */
const uint32_t BPP_DRAIN_DISABLE   = 1<<20; /* <-> Disable draining cache */
const uint32_t BPP_TC_INTR_DISABLE = 1<<23; /* <-> Disable terminal count inter. */
const uint32_t BPP_EN_CHAIN_DMA    = 1<<24; /* <-> Enable chained dma */
const uint32_t BPP_DMA_ON          = 1<<25; /*  -> DMA is on */
const uint32_t BPP_ADDR_VALID      = 1<<26; /*  -> addr and bcnt are valid */
const uint32_t BPP_NEXT_VALID      = 1<<27; /*  -> next addr and bcnt valid */
const uint32_t BPP_DEVICE_ID_MASK  = 0xf0000000;

/* Cf. /usr/include/sys/bpp_reg.h  for the original version. */
/* Bits in the hw_config register */
const uint16_t BPP_DSS_SIZE = (1<< 6)|(1<< 5)|(1<< 4)|(1<< 3)|(1<< 2)|(1<<1)| 1;
const uint16_t BPP_DSW_SIZE = (1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8);
const uint16_t BPP_CNTR_TEST= (1<<15);

/* Cf. /usr/include/sys/bpp_reg.h  for the original version. */
/* Bits in the op_config register */
const uint16_t BPP_EN_VERSATEC       = 1;     /* Enable versatec operation (Zebra) */
const uint16_t BPP_VERSATEC_INTERLOCK= 1<< 1; /* Versatec connector absent (Zebra) */
const uint16_t BPP_IDLE              = 1<< 3; /* data transfer idle */
const uint16_t BPP_SRST              = 1<< 7; /* reset state machines */
const uint16_t BPP_ACK_OP            = 1<< 8; /* Acknowledge handshake op */
const uint16_t BPP_BUSY_OP           = 1<< 9; /* Busy handshake op */
const uint16_t BPP_EN_DIAG           = 1<<10; /* Enable diagnostic mode */
const uint16_t BPP_ACK_BIDIR         = 1<<11; /* Acknowledge is bidirectional */
const uint16_t BPP_BUSY_BIDIR        = 1<<12; /* Busy is bidirectional */
const uint16_t BPP_DS_BIDIR          = 1<<13; /* Data Strobe is bidirectional */
const uint16_t BPP_DMA_DATA          = 1<<14; /* Data value in DMA mem clear */
const uint16_t BPP_EN_MEM_CLR        = 1<<15; /* Enable DMA memory clear op */

/* Cf. /usr/include/sys/bpp_reg.h  for the original version. */
/* Bits in the trans_cntl register */
const uint8_t BPP_DS_PIN    = 1;      /* ControlerEnable/Data Strobe pin */
const uint8_t BPP_ACK_PIN   = 1<< 1;  /* Input#2/Acknowledge pin */
const uint8_t BPP_BUSY_PIN  = 1<< 2;  /* Input#1/Busy pin */
const uint8_t BPP_DIRECTION = 1<< 3;  /* Direction control, 0 == write */

/* Cf. /usr/include/sys/bpp_io.h  for the original version. */
/* Bits in the out_pins register */
const uint8_t BPP_SLCTIN_PIN = 1;     /* Output#1/Select in pin */
const uint8_t BPP_AFX_PIN    = 1<< 1; /* Output#2/Auto feed pin */
const uint8_t BPP_INIT_PIN   = 1<< 2; /* Standby/Initialize pin */

/* Cf. /usr/include/sys/bpp_io.h  for the original version. */
/* Bits in the in_pins register */
const uint8_t BPP_ERR_PIN  = 1;       /* Input#3/Error pin */
const uint8_t BPP_SLCT_PIN = 1<< 1;   /* Switch2/Select pin */
const uint8_t BPP_PE_PIN   = 1<< 2;   /* Switch1/Paper empty pin */

/* Cf. /usr/include/sys/bpp_reg.h  for the original version. */
/* Bits in the int_cntl register */
const uint16_t BPP_ERR_IRQ_EN = 1;     /* Input#3/ERR interrupt enable */
const uint16_t BPP_ERR_IRP    = 1<< 1; /* Input#3/ERR polarity: 1=rising edge */
const uint16_t BPP_SLCT_IRQ_EN= 1<< 2; /* Switch2/SLCT interrupt enable */
const uint16_t BPP_SLCT_IRP   = 1<< 3; /* Switch2/SLCT polarity: 1=rising edge */
const uint16_t BPP_PE_IRQ_EN  = 1<< 4; /* Switch1/PE interrupt enable */
const uint16_t BPP_PE_IRP     = 1<< 5; /* Switch1/PE polarity: 1=rising edge */
const uint16_t BPP_BUSY_IRQ_EN= 1<< 6; /* Input#1/BUSY interrupt enable */
const uint16_t BPP_BUSY_IRP   = 1<< 7; /* Input#1/BUSY polarity: 1=rising edge */
const uint16_t BPP_ACK_IRQ_EN = 1<< 8; /* Input#2/ACK interrupt enable  */
const uint16_t BPP_DS_IRQ_EN  = 1<< 9; /* ControlerEnable/DS interrupt enable */
const uint16_t BPP_ERR_IRQ    = 1<<10; /* Input#3/ERR interrupt pending */
const uint16_t BPP_SLCT_IRQ   = 1<<11; /* Switch2/SLCT interrupt pending */
const uint16_t BPP_PE_IRQ     = 1<<12; /* Switch1/PE interrupt pending */
const uint16_t BPP_BUSY_IRQ   = 1<<13; /* Input#1/BUSY interrupt pending */
const uint16_t BPP_ACK_IRQ    = 1<<14; /* Input#2/ACK interrupt pending */
const uint16_t BPP_DS_IRQ     = 1<<15; /* ControlerEnable/DS interrupt pending */
#define BPP_ALL_IRQS (BPP_ERR_IRQ | BPP_SLCT_IRQ | BPP_PE_IRQ | BPP_BUSY_IRQ \
                                  | BPP_ACK_IRQ | BPP_DS_IRQ)

#ifdef __cplusplus
}
#endif

#endif

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